| 摘要 |
An output enable signal generating circuit according to the present technology includes: a sensing unit which outputs a control signal which is enabled when a CAS latency signal is changed; an output reset signal generating unit which outputs an output reset signal in response to the control signal; and an output enable signal generating unit which is reset in response to the output reset signal and outputs a read command as the output enable signal by measuring the delay amount of an internal clock signal. [Reference numerals] (110) Sensing unit; (120) Output reset signal generating unit; (130) Output enable signal generating unit |
