发明名称 |
Pattern layout in semiconductor device |
摘要 |
According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below. |
申请公布号 |
US8618665(B2) |
申请公布日期 |
2013.12.31 |
申请号 |
US201113234170 |
申请日期 |
2011.09.16 |
申请人 |
SHIKATA GO;NAKAJIMA FUMIHARU;EDAHIRO TOSHIAKI;KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIKATA GO;NAKAJIMA FUMIHARU;EDAHIRO TOSHIAKI |
分类号 |
H01L23/48;G11C7/06 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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