发明名称 |
DETERMINISTIC CLOCK CROSSING |
摘要 |
Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock. |
申请公布号 |
US2013326205(A1) |
申请公布日期 |
2013.12.05 |
申请号 |
US201113995274 |
申请日期 |
2011.12.22 |
申请人 |
KULICK STANLEY STEVE;FRANCOM ERIN;BESSETTE JASON |
发明人 |
KULICK STANLEY STEVE;FRANCOM ERIN;BESSETTE JASON |
分类号 |
G06F1/06;G06F1/24 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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