发明名称 |
Integrated circuit method with triple patterning |
摘要 |
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features. |
申请公布号 |
US8562843(B2) |
申请公布日期 |
2013.10.22 |
申请号 |
US201113276168 |
申请日期 |
2011.10.18 |
申请人 |
LIU CHIA-CHU;CHEN KUEI SHUN;CHEN MENG WEI;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIU CHIA-CHU;CHEN KUEI SHUN;CHEN MENG WEI |
分类号 |
H01B13/00 |
主分类号 |
H01B13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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