发明名称 DELAY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a delay circuit that can suppress an increase in circuit scale.SOLUTION: According to one embodiment, a delay circuit 1 comprises: a transistor Tr11 that causes a gate leakage current to flow to a gate when an external input signal IN is supplied to at least any one of a source, a drain and a back gate; a transistor Tr12 for removing an AC component of the external input signal IN propagating to the gate of the transistor Tr11 via a coupling capacitance formed by the transistor Tr11; and inverters 12, 13 for detecting a voltage value based on the gate leakage current and outputting a detection result of a logic value depending on the voltage value as an external output signal OUT.
申请公布号 JP2013207659(A) 申请公布日期 2013.10.07
申请号 JP20120076386 申请日期 2012.03.29
申请人 RENESAS ELECTRONICS CORP 发明人 KOSUGE YOSHIHIRO
分类号 H03K5/14 主分类号 H03K5/14
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