SEMICONDUCTOR MEMORY DEVICE HAVING POWER DECOUPLING CAPACITOR

摘要

PURPOSE: A semiconductor memory device having a power decoupling capacitor is provided to minimize a decrease in effective capacitance by reducing the resistance element of a plate electrode. CONSTITUTION: A cell array region (A) includes a bit line and a cell capacitor (102). The bit line is electrically connected to a source/drain region. A peripheral circuit region (B) includes decoupling capacitors (104a-104f). The decoupling capacitors and the cell capacitor are formed on the same level. A metal line layer is electrically connected to a conductive layer.