发明名称 PACKET TRANSFER DELAY MEASUREMENT SYSTEM
摘要 PROBLEM TO BE SOLVED: To measure one-way packet transfer delay in confronted first and second measurement devices in a time asynchronous manner.SOLUTION: A first measurement device includes: means for generating a plurality of first packets including first counter values on transmission by a first counter interlocked with a first built-in clock to transmit them when a traffic is not congested; and means for generating a second packet including a second counter value on transmission by the first counter. A second measurement device includes: means for calculating an increase ratio of the first counter value and a third counter value per unit time on the basis of the first counter value extracted from the first packet, the third counter value on reception by a second counter interlocked with a second built-in clock and reception time information; and means for calculating an expected fourth counter value on reception on the basis of the second counter value extracted from the second packet and the increase ratio and obtaining one-way packet transfer delay on the basis of the calculated expected fourth counter value and an actual fourth counter value on reception.
申请公布号 JP2013175894(A) 申请公布日期 2013.09.05
申请号 JP20120038605 申请日期 2012.02.24
申请人 FUJITSU LTD 发明人 SUZUKI YASUHIRO
分类号 H04L12/70 主分类号 H04L12/70
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