发明名称 Method of forming a via and method of fabricating chip stack package thereof
摘要 <p>A via forming method that includes forming via-holes in a substrate is provided. The method includes putting the substrate, having the via-holes, in a first solution to fill the via-holes with the first solution. Metal particles are sunk into the via-holes by supplying a second solution containing the metal particles to the first solution. A first curing process of heat-treating the substrate is performed so as to form vias in the via-holes. A multi-chip package that includes the substrate having the vias is also provided.</p>
申请公布号 KR101302564(B1) 申请公布日期 2013.09.02
申请号 KR20090102999 申请日期 2009.10.28
申请人 发明人
分类号 H01L21/288;H01L21/60;H01L23/12;H01L23/48 主分类号 H01L21/288
代理机构 代理人
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