发明名称 PIPELINE ARCHITECTURE FOR SCALABLE PERFORMANCE ON MEMORY
摘要 An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
申请公布号 KR20130095303(A) 申请公布日期 2013.08.27
申请号 KR20137015324 申请日期 2011.11.07
申请人 INTEL CORP. 发明人 SUNDARAM RAJESH;KAU DERCHANG;ZIMMERMAN DAVID J.
分类号 G11C13/02 主分类号 G11C13/02
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