| 摘要 |
<p>According to this method, a carry generation command (M) is applied repetitively to a command input (G) of a carry-propagation logic circuit (1), the application of said command (M) to said input (G) is timed by means of a reference clock signal (CLKR), the application to said input (G) of a command to erase the last carry applied to said input is timed by means of said reference clock signal (CLKR), said logic circuit (1) is commanded to propagate said carry generated and the consecutive erasure of said carry generated up to a carry output (C) of said logic circuit (1), the command (M) is modified from one cycle to another of said reference clock signal (CLKR) so as to vary the duration of propagation of said carry in said logic circuit (1), and said variable clock signal (CLKV) is generated on the basis of the logic state present on said carry output (C).</p> |
