In one embodiment a system comprises an integrated circuit, a plurality of voltage regulators; and a data bus coupled to the integrated circuit and the plurality of voltage regulators. In some embodiments the integrated circuit comprises logic to embed a timing signal on the data bus. Other embodiments may be described.
申请公布号
WO2013106206(A1)
申请公布日期
2013.07.18
申请号
WO2012US71993
申请日期
2012.12.28
申请人
INTEL CORPORATION;IYER, JAYESH;STANFORD, EDWARD R.;KRAIPAK, WASEEM
