发明名称 |
Resistive Memory and Methods for Forming the Same |
摘要 |
A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
|
申请公布号 |
US2013161707(A1) |
申请公布日期 |
2013.06.27 |
申请号 |
US201113335569 |
申请日期 |
2011.12.22 |
申请人 |
HUANG CHIA-EN;LIN WUN-JIE;HU LING-CHANG;YANG HSIAO-LAN;CHIU CHIH-CHIEH;KAO WEI-SHUO;CHENG HONG-CHEN;WU FU-AN;YANG JUNG-PING;LEE CHENG HUNG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUANG CHIA-EN;LIN WUN-JIE;HU LING-CHANG;YANG HSIAO-LAN;CHIU CHIH-CHIEH;KAO WEI-SHUO;CHENG HONG-CHEN;WU FU-AN;YANG JUNG-PING;LEE CHENG HUNG |
分类号 |
H01L29/78;H01L21/336 |
主分类号 |
H01L29/78 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|