发明名称 CMOS OUTPUT VOLTAGE LIMITER
摘要 PURPOSE: A CMOS output voltage limit circuit is provided to provide a CMOS output voltage limit circuit which is suitable for a CMOS process by implementing all components in the CMOS process. CONSTITUTION: A comparator generates a comparison signal by comparing a voltage of an input signal with a limit voltage. The comparison signal has a logic state according to a comparison result of the limit voltage and the voltage of the input signal. According to the logic state of the comparison signal, a switching unit outputs any one of the input signal and the limit voltage as a selection signal. An amplifier generates an output signal by amplifying the selection signal.
申请公布号 KR20130063055(A) 申请公布日期 2013.06.14
申请号 KR20110129353 申请日期 2011.12.06
申请人 TLI INC. 发明人 CHOI, JUNG YEOL
分类号 H04N5/374;H01L27/146 主分类号 H04N5/374
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