CLOCK GENERATION CIRCUIT, METHOD OF CONTROLLING THE SAME, EMULATOR, AND EMULATION METHOD

摘要

PROBLEM TO BE SOLVED: To eliminate a period during which all of output clock signals do not change when the plurality of output clock signals having different division ratios are output from an input clock.

SOLUTION: A clock generation circuit is for emulation of a semiconductor integrated circuit. The clock generation circuit comprises: a plurality of clock frequency divider circuits 270 to 290 that divide an identical input clock signal by different division ratios; and a minimum value selection unit 236 that is connected to the plurality of clock frequency divider circuits 270 to 290. Each of the plurality of clock frequency divider circuits 270 to 290 includes a clock interval acquisition unit 235 and a skip unit 237. The clock interval acquisition unit 235 obtains a state change interval between a current state and the next state change in the output clock signal after frequency division. The minimum value selection unit 236 selects a minimum value out of a plurality of state change intervals that are obtained by the plurality of clock frequency divider circuits 270 to 290. The skip unit 237 advances the output clock signal by the selected minimum value.

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