发明名称 RESET SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME
摘要 <P>PROBLEM TO BE SOLVED: To provide a reset signal generation circuit that can activate a reset signal during a period between power-on and the first activation of an external reset signal. <P>SOLUTION: A reset signal generation circuit 101 of the present invention comprises: an external reset detection circuit 102 that detects the first activation of an external reset signal; and a control circuit that activates a reset signal irrespective of the external reset signal if the detection result of the external reset detection circuit 102 indicates that the first activation of the external reset signal is yet to be performed. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013105449(A) 申请公布日期 2013.05.30
申请号 JP20110250923 申请日期 2011.11.16
申请人 RENESAS ELECTRONICS CORP 发明人 AKIYAMA YUSUKE
分类号 G06F1/24;H03K17/22 主分类号 G06F1/24
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