MULTI DIE PACKAGE STRUCTURES

摘要

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi chip modules), systems on chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic to memory, memory to memory, and logic to logic interface stacking assemblies.