| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an XOR gate circuit that has a reduced number of elements, a small delay and a driver capability. <P>SOLUTION: A logic circuit 1 includes: a transistor T1 connected between a supply potential VPERI and a node n1; a transistor T2 connected between the supply potential VPERI and a node n2; a transistor T3 connected between a supply potential VSS and a node n3; a transistor T4 connected between the supply potential VSS and a node n4; transistors T5, T7 connected in series between the node n1 and the node n3; transistors T9, T11 connected in series between the node n1 and the node n3; transistors T6, T8 connected in series between the node n2 and the node n4; and transistors T10, T12 connected in series between the node n2 and the node n4. An output signal Y is taken from a junction of the transistors T5, T7 and a junction of the transistors T6, T8. <P>COPYRIGHT: (C)2013,JPO&INPIT |
