发明名称 |
Methods and Circuits for Duty-Cycle Correction |
摘要 |
A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.
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申请公布号 |
US2013063191(A1) |
申请公布日期 |
2013.03.14 |
申请号 |
US201213612540 |
申请日期 |
2012.09.12 |
申请人 |
PATIL DINESH;HEKMAT MOHAMMAD;KAVIANI KAMBIZ;AMIRKHANY AMIR;RAMBUS INC. |
发明人 |
PATIL DINESH;HEKMAT MOHAMMAD;KAVIANI KAMBIZ;AMIRKHANY AMIR |
分类号 |
H03K3/017;H03L7/08 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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