发明名称 |
Supplying a clock signal and a gated clock signal to synchronous elements |
摘要 |
A clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The circuitry receives a clock signal, a clock enable signal having either an enable value or a disable value, and a power mode signal having either a low power value (indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down), or a functional mode value (indicating the plurality of synchronous elements are to be powered). A clock gating unit has logic circuitry that is configured to output the clock signal or the predetermined gated value depending upon the low power value and the functional mode value.
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申请公布号 |
US8390328(B2) |
申请公布日期 |
2013.03.05 |
申请号 |
US201113067184 |
申请日期 |
2011.05.13 |
申请人 |
MYERS JAMES EDWARD;FLYNN DAVID WALTER;AITKEN ROBERT CAMPBELL;FREDERICK, JR. MARLIN WAYNE;ARM LIMITED |
发明人 |
MYERS JAMES EDWARD;FLYNN DAVID WALTER;AITKEN ROBERT CAMPBELL;FREDERICK, JR. MARLIN WAYNE |
分类号 |
H03K19/00 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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