发明名称 |
Verification of 3D integrated circuits |
摘要 |
A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.
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申请公布号 |
US8359554(B2) |
申请公布日期 |
2013.01.22 |
申请号 |
US201113274091 |
申请日期 |
2011.10.14 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;WANG CHUNG-HSING;TSAI CHIH SHENG;LIU YING-LIN;LIN KAI-YUN |
发明人 |
WANG CHUNG-HSING;TSAI CHIH SHENG;LIU YING-LIN;LIN KAI-YUN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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