发明名称 |
Interconnect Structure for Wafer Level Package |
摘要 |
A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
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申请公布号 |
US2013001776(A1) |
申请公布日期 |
2013.01.03 |
申请号 |
US201113170973 |
申请日期 |
2011.06.28 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;YU CHEN-HUA;LIN JING-CHENG;LIU NAI-WEI;HUNG JUI-PIN;JENG SHIN-PUU |
发明人 |
YU CHEN-HUA;LIN JING-CHENG;LIU NAI-WEI;HUNG JUI-PIN;JENG SHIN-PUU |
分类号 |
H01L23/485;H01L21/28 |
主分类号 |
H01L23/485 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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