发明名称 Fast repeater latch
摘要 A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled to the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state of the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal.
申请公布号 US8330588(B2) 申请公布日期 2012.12.11
申请号 US20100759833 申请日期 2010.04.14
申请人 DIXIT ANAND;MAISLEID ROBERT P.;ORACLE INTERNATIONAL CORPORATION 发明人 DIXIT ANAND;MAISLEID ROBERT P.
分类号 G08B1/00;H03L7/00 主分类号 G08B1/00
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