发明名称
摘要 The circuit comprises E-mode transistors (E3, E4, E5) with gate-source junction, a D-mode transistor (D) with gate-source junction, a component generating a voltage drop (E1, E2) between the source (4) of the D-mode transistor and the drain (2) of an E-mode transistor provided as a signal output (OUT), a connection (7) between this drain (2) of the E-mode transistor and the gate (6) of the D-mode transistor, and a signal input (IN) at the gates (3, 24, 27) of the E-mode transistors. The E-mode transistors are arranged to operate as NAND and/or NOR logics. The circuit enables the operation of logic circuitry in GaAs technology with only low currents flowing.
申请公布号 JP2012530442(A) 申请公布日期 2012.11.29
申请号 JP20120515461 申请日期 2010.06.15
申请人 发明人
分类号 H03K19/0944;H03K19/20 主分类号 H03K19/0944
代理机构 代理人
主权项
地址