发明名称 Flop type selection for very large scale integrated circuits
摘要 A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.
申请公布号 US8305126(B2) 申请公布日期 2012.11.06
申请号 US201113005835 申请日期 2011.01.13
申请人 SMITH ALAN P.;MASLEID ROBERT P.;KONSTADINIDIS GEORGIOS;ORACLE INTERNATIONAL CORPORATION 发明人 SMITH ALAN P.;MASLEID ROBERT P.;KONSTADINIDIS GEORGIOS
分类号 H03K3/289;G01R35/00 主分类号 H03K3/289
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