发明名称 vMOS Multi-valued Counter Unit
摘要 The present invention discloses a &ngr;MOS based multi-valued counter unit. The counter unit includes a &ngr;MOS source follower and at least a control gate connected the &ngr;MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the &ngr;MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the &ngr;MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).
申请公布号 US2012250817(A1) 申请公布日期 2012.10.04
申请号 US201213488970 申请日期 2012.06.05
申请人 WANG PENG JUN;ZHANG YUE JUN;NINGBO UNIVERSITY 发明人 WANG PENG JUN;ZHANG YUE JUN
分类号 H03K23/00 主分类号 H03K23/00
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