SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR CHIP, AND DESIGN APPROACH OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which clock skew is suppressed with a small scale configuration by a simple design.

SOLUTION: Between the data input terminals of latch circuits 31-316and a supply source PD of data bit, first delay sections 51, 52 consisting of a series connection of logic elements of the same number as that of the logic elements included in the clock signal path between the supply source PCD of clock signal CLL and the clock input terminals of the latch circuits, and a second delay section 53 having a delay time of the same length as that of the wiring delay time corresponding to the length of wiring in the clock signal path are provided.

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