发明名称 Designing method of semiconductor integrated circuit
摘要 A designing method of a semiconductor integrated circuit is provided, the method including a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping an output signal from the logic circuit according to a clamp control signal; and a generation step of generating, in order to verify the first design data, second design data in which a first mask circuit for masking the output signal from the logic circuit according to the power gating control signal is added in place of the power gating circuit to the first design data.
申请公布号 US8250504(B2) 申请公布日期 2012.08.21
申请号 US20090556649 申请日期 2009.09.10
申请人 SHIKATA TAKASHI;FUJITSU SEMICONDUCTOR LIMITED 发明人 SHIKATA TAKASHI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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