| 摘要 |
Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B.
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