| 摘要 |
<p>A system and method to reduce power consumption in electronic devices is disclosed. The structures and methods can be implemented largely by reusing bulk CMOS process flows and manufacturing technology. The structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set more precisely. The DDC design also has a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption.</p> |
