MULTICORE SYSTEM AND MEMORY MANAGEMENT DEVICE FOR MULTICORE SYSTEM

摘要

PURPOSE: A multi-core system and a memory management device thereof are provided to reduce unnecessary network traffic and simplify a system structure by selectively loading a page which is accessed by a processor on a cache. CONSTITUTION: A first TLB(Translation Lookaside Buffer) exception processor(211) duplicates a page descriptor having a loading location determining field to a TLB of a first processor. The TLB indicates a page which the first processor accesses and indicates wether the page is loaded to a cache of the first processor from a memory area. If the page is a write-shared page, a second TLB exception processor(212) transfers an interrupt message to the second processor.