| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a gate drive circuit capable of reducing variations in a transmission delay time of a gate drive signal. <P>SOLUTION: A gate drive circuit 1 comprises: a transformer drive circuit part 3 which drives a transformer 2; a timing generation part 4 which generates primary side drive timing of the transformer 2 and sets a primary side drive voltage change rate of the transformer 2 to be different in an ON state and OFF state of an input gate drive signal; a differentiation circuit part 5 which detects a secondary side voltage change rate of the transformer 2 by differentiating a secondary side voltage of the transformer 2; a level detection circuit part 6 which detects a differential value level of the input gate drive signal in the OFF state; a level detection circuit part 7 which detects the differential value level of the input gate drive signal in the ON state; and a flip-flop circuit part 8 which has an R terminal and an S terminal connected to the level detection circuit parts 6, 7, and generates and holds an output gate drive signal. <P>COPYRIGHT: (C)2012,JPO&INPIT |
