Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs

摘要

Various aspects described herein create tessellated regions by identifying tessellation lines in one or more directions based at least on fixed shape(s) or route(s). New cells or shapes are added to the design by aligning at least some of the boundary segments of the new cells or shapes with existing tessellation lines. Tessellation lines are dynamically adjustable. At least some tessellated regions are associated with initial or tentative track pattern labels some of which are iteratively updated during implementation of the design. Multiple candidate track patterns may be ranked based on consistency costs to determine a tentative track pattern. Designs may be implemented with a trackless approach in trackless region(s) followed by a tracked approach based at least in part upon the initial or tentative labels that are dynamically adjusted during implementation. Capacities and demands are assessed at boundary segments of cells by using the tracked or trackless approach.

主权项

1. A computer implemented method for tessellating and labeling routing space for routing electronic designs, comprising:
using a computing system having at least one processor or at least one processor core to perform a process, the process comprising: creating, at a tessellation mechanism including or functioning in tandem with the at least one processor, routing grids that define multiple tessellated regions for at least a portion of a layer of an electronic design; determining, at a region labeling mechanism coupled with the tessellation mechanism, a tentative track pattern label by identifying the tentative track pattern label from multiple track pattern labels for at least one tessellated region of the multiple tessellated regions based in part or in whole upon one or more criteria, wherein the tentative track pattern label indicates which track pattern comprising an arrangement of tracks in a permissible order is to be used for physical implementation of the at least one tessellated region; and performing, at one or more routing mechanisms including or function in tandem with the at least one processor and coupled with the region labeling mechanism, routing for the portion of the layer by referencing the tentative track pattern label for the at least one tessellated region to interconnect circuit component designs in the layer of the electronic design.