HARDWARE ASSISTED PERFORMANCE STATE MANAGEMENT BASED ON PROCESSOR STATE CHANGES

摘要

A processor is configured to support a plurality of performance states and idle states. The processor includes a first programmable location associated with a first idle state and configured to store first entry performance state (P-State) information. The first entry P-State information identifies a first entry P-State. The processor is configured to receive a request to enter the first idle state, retrieve the first entry P-State information and enter the first entry P-State. The processor may include a second programmable location associated with the first idle state and configured to store first exit P-State information. The first exit P-State information identifies a first exit P-State. The processor may be configured to receive a request to exit the first idle state, retrieve the first exit P-State information and enter the first exit P-State.