| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce variation in a pinch-off voltage of a J-FET (Junction Field Effect Transistor), and to realize a low pinch-off voltage. <P>SOLUTION: An N type epitaxial layer 6 is deposited on a P type semiconductor substrate 5. An N+ type source layer 3 is formed on a surface of the N type epitaxial layer 6. A pair of P+ type gate layers 2a and 2b is formed on the surface of the N type epitaxial layer 6 so as to surround the N+ type source layer 3. An N+ type drain layer 1 is formed on the surface of the N type epitaxial layer 6 in a region separated from the P+ type gate layer 2b. <P>COPYRIGHT: (C)2012,JPO&INPIT |
