| 摘要 |
TFTs 10 and 15 and the organic EL device 17 are provided between a power line Vp and a common cathode Vcom, and a capacitor 16 and a TFT 11 are provided between a gate of the TFT 10 and a data line Sj. A TFT 12 is provided between the gate and a drain of the TFT 10, a TFT 13 is provided between an anode terminal of the organic EL device 17 and the common cathode Vcom, and a TFT 14 is provided between one electrode of the capacitor 16 and the power line Vp. Gates of the TFTs 11 to 13 are connected to a scanning line Gi, and gates of the TFTs 14 and 15 are connected to a scanning line Ei. When writing, a high potential is supplied to the scanning line Gi, and a low potential is supplied to the scanning line Ei a little after this. While the high potentials are supplied to the two scanning lines, the data line Sj is controlled to be in a high impedance state. In this manner, a pixel circuit configured by N-type transistors is driven using two types of scanning lines. |
