发明名称 STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI
摘要 A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
申请公布号 US2012142166(A1) 申请公布日期 2012.06.07
申请号 US201213366143 申请日期 2012.02.03
申请人 HUDAIT MANTU K.;SHAHEEN MOHAMAD A.;CHOW LOREN A.;TOLCHINSKY PETER G.;FASTENAU JOEL M.;LOUBYCHEV DMITRI;LIU AMY W.K. 发明人 HUDAIT MANTU K.;SHAHEEN MOHAMAD A.;CHOW LOREN A.;TOLCHINSKY PETER G.;FASTENAU JOEL M.;LOUBYCHEV DMITRI;LIU AMY W.K.
分类号 H01L21/20 主分类号 H01L21/20
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