发明名称 CLOCK TREE GENERATION APPARATUS AND CLOCK TREE GENERATION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To appropriately settle a timing error by easily adjusting clock delay or the like. <P>SOLUTION: A clock tree generation apparatus includes acquisition means which acquires information on a clock tree and information on a plurality of clocks that a plurality of flip-flops included in the clock tree use, flip-flop number specification means which specifies the number of flip-flops to be driven by each clock for each of the plurality of clocks acquired by the acquisition means, clock specification means which specifies only a predetermined number of high-order clocks with a little flip-flops among the plurality of clocks on the basis of the number of flip-flops for each of the plurality of clocks specified by the flip-flop number specification means, and division means which divides the clock tree with the flip-flops to be driven by the clock specified by the clock specification means as a criterion. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012094065(A) 申请公布日期 2012.05.17
申请号 JP20100242588 申请日期 2010.10.28
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 SHIGIHARA YASUJI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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