发明名称 |
CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD |
摘要 |
A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.
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申请公布号 |
US2012115279(A1) |
申请公布日期 |
2012.05.10 |
申请号 |
US201213347543 |
申请日期 |
2012.01.10 |
申请人 |
BONTHRON ANDREW J.;WALWORTH DARREN JAY;SEMTECH CORPORATION |
发明人 |
BONTHRON ANDREW J.;WALWORTH DARREN JAY |
分类号 |
H01L21/50 |
主分类号 |
H01L21/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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