发明名称 Image data transfer circuit
摘要 An image data transfer circuit and an image data transfer method capable of exception processing without affecting image data of normal frames when an error is detected in image data. Image data applied to an input processing section is filtered by a filter, stored in an FIFO buffer, and sequentially read from an output section for transfer to the outside. In this event, two frame counters count numbers of frames which are being processed in input processing and output processing, respectively. When an error is detected in the input processing section, a stop controller does not output a stop request signal if the two count values do not match, and outputs the stop request signal at the time the two count values match. In this way, operations on error data are stopped after all image data of normal frames stored in the FIFO buffer has been transferred to the outside.
申请公布号 US8165225(B2) 申请公布日期 2012.04.24
申请号 US20070703668 申请日期 2007.02.08
申请人 ISHIDA KEITARO;LAPIS SEMICONDUCTOR CO., LTD. 发明人 ISHIDA KEITARO
分类号 H04N7/64 主分类号 H04N7/64
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