发明名称 |
Method and system for instruction address parity comparison |
摘要 |
A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value. |
申请公布号 |
US8140951(B2) |
申请公布日期 |
2012.03.20 |
申请号 |
US20080031732 |
申请日期 |
2008.02.15 |
申请人 |
BUSABA FADI Y.;PRASKY BRIAN R.;SHUM CHUNG-LUNG KEVIN;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUSABA FADI Y.;PRASKY BRIAN R.;SHUM CHUNG-LUNG KEVIN |
分类号 |
G06F11/00;H03M13/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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