发明名称 |
Pattern verification method, program thereof, and manufacturing method of semiconductor device |
摘要 |
A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern. |
申请公布号 |
US8127265(B2) |
申请公布日期 |
2012.02.28 |
申请号 |
US201113067567 |
申请日期 |
2011.06.09 |
申请人 |
OGAWA RYUJI;HASHIMOTO KOJI;KABUSHIKI KAISHA TOSHIBA |
发明人 |
OGAWA RYUJI;HASHIMOTO KOJI |
分类号 |
G06F17/50;G03F1/36;G03F1/68;G03F1/70;H01L21/027;H01L21/82 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|