发明名称
摘要 <p>A flat panel display capable of reducing element defects by decreasing taper angles of contact holes and a via hole. The flat panel display includes a thin film transistor having at least source and drain electrodes formed over an insulating substrate, an insulating layer having a via hole for exposing one of the source and drain electrodes, and an anode connected to said one of the source and drain electrodes through the via hole. The via hole and the anode are tapered with taper angles of 60 DEG or less. The source and drain electrodes are connected respectively to source and drain regions of the thin film transistor through the contact holes. The contact holes are also tapered with taper angles of 60 DEG or less. <IMAGE></p>
申请公布号 JP4879478(B2) 申请公布日期 2012.02.22
申请号 JP20040344946 申请日期 2004.11.29
申请人 发明人
分类号 H01L21/28;H05B33/02;H01L21/768;H01L21/77;H01L21/84;H01L27/12;H01L27/32;H01L29/417;H01L29/786;H01L51/50;H01L51/52;H05B33/22 主分类号 H01L21/28
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