| 摘要 |
Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.
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