发明名称 MEMORY TRANSACTION BURST OPERATION FOR SUPPORTING TIME-MULTIPLEXED ERROR CORRECTION CODING AND MEMORY COMPONENT
摘要 <P>PROBLEM TO BE SOLVED: To avoid a request to a dedicated ECC memory device and a dedicated ECC bit lane. <P>SOLUTION: Error correction coding data is time-multiplexed to user data on the same data bus line (DQ1-DQn) in a burst mode transfer. A memory device on a module each includes an ECC segment which is associated with a segment that can designate the address of the device, and can further indirectly designate the address. The time-multiplexed ECC data is read and written from/to an indirect address designatable segment associated with address designation data transferred in a burst mode transfer. Further, two types of burst modes are supported: one includes ECC data, and the other does not include the ECC data. Although one type of a memory module supports both an ECC system and a non-ECC system and uses an ECC for the same data, the one type of a memory module can not be used for another data of the same system. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011243206(A) 申请公布日期 2011.12.01
申请号 JP20110115561 申请日期 2011.05.24
申请人 INTEL CORP 发明人 PETE VOGT
分类号 G06F12/16;G06F12/04;G11C11/401 主分类号 G06F12/16
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