发明名称 |
Method and Apparatus for Merging EDA Coverage Logs of Coverage Data |
摘要 |
An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model. |
申请公布号 |
US2011283246(A1) |
申请公布日期 |
2011.11.17 |
申请号 |
US201113189314 |
申请日期 |
2011.07.22 |
申请人 |
BIST MANOJ;MEHROTRA SANDEEP;SYNOPSYS, INC. |
发明人 |
BIST MANOJ;MEHROTRA SANDEEP |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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