| 摘要 |
PROBLEM TO BE SOLVED: To improve digital signal processing performance while suppressing increase in circuit scale, in a receiver provided in a high-speed interface.SOLUTION: The receiver includes: a digital/analog conversion part which converts voltage change of an analog signal to be input into a series of digital data; a parallelization part which parallelizes the series of the digital data; an equalizer part which performs waveform generation processing on parallelized digital signals; a delay addition part which branches an analog signal into a plurality of lines to give different delays to the plurality of lines of analog signals, respectively; and a gain control part which controls a gain of an amplifier in which the analog signals of each line delayed by the delay addition part are input by bias current of the amplifier. |
