Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider

摘要

A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.