发明名称 Voltage regulator for a synchronous clock system to reduce clock tree jitter
摘要 A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.
申请公布号 US8026701(B2) 申请公布日期 2011.09.27
申请号 US20080265908 申请日期 2008.11.06
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM HYUNG-SOO;KIM YONG-JU;HAN SUNG-WOO;SONG HEE-WOONG;OH IC-SU;HWANG TAE-JIN;CHOI HAE-RANG;LEE JI-WANG;JANG JAE-MIN;PARK CHANG-KUN
分类号 G05F1/652 主分类号 G05F1/652
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