发明名称 Processor for executing highly efficient VLIW
摘要 A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
申请公布号 US8019971(B2) 申请公布日期 2011.09.13
申请号 US20090418965 申请日期 2009.04.06
申请人 PANASONIC CORPORATION 发明人 TAKAYAMA SHUICHI;HIGAKI NOBUO
分类号 G06F15/80;G06F9/30;G06F9/318;G06F9/38 主分类号 G06F15/80
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