DLL HAVING 2-PHASE DELAY LINE AND DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF

摘要

Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line.